The present invention relates to the field of electronic circuits, and, more particularly, to programmable logic devices.
Configurable memories are embedded in field programmable logic devices to provide on-chip fast random access memory (RAM). There are two types of memory resources commercially available, which are illustratively shown in FIG. 1. The first is the look-up table (LUT) type, which are found inside logic blocks 102 of FIG. 1. These may be combined in various configurations to provide memories of varying widths and depths, such as in the Xilinx XC4000 and Virtex devices, for example.
One drawback of such distributed memory resources is that the large memory formed by combining these resources may be relatively slow. Moreover, one has to provide read/write control circuitry for all of the LUTs. Further, if these LUTs are not used to implement memory, then the read/write control circuitry associated therewith is wasted.
The second type of on-chip memory resource includes large xe2x80x9cblocksxe2x80x9d of RAM bits 101, such as those provided by Xilinx and Altera. These can be configured to provide memories with varying widths and depths. Yet, one drawback associated with using blocks of RAM bits is that if a block (e.g., 4 k) is used to implement a small memory (e.g., 512xc3x972)), then a significant amount of unused RAM bits (i.e., 3 K) will be wasted. Moreover, if a logical memory supports an odd width (e.g., 256xc3x979), then even more resources are wasted.
U.S. Pat. No. 5,801,547 describes embedded memory structures of the same type which may be combined and configured independently. As such, these memory structures may similarly suffer from the above-described drawbacks.
The present invention provides a field programmable logic device including at least two independently configurable embedded memory structures. The memory structures differ in parameters such as memory size, available configuration depths, and/or available configuration widths to provide for a more efficient memory utilization.
More particularly, the memory structures may provide mutually exclusive configuration options in at least one configuration parameter. The memory structures may be combined to form larger configurations through interconnection of dedicated memory routing tracks and horizontal routing channels, where the dedicated memory routing tracks may include a plurality of bus-based vertical tracks originating from memory I/Os. Further, horizontal routing channels may include several routing tracks.
The dedicated memory routing track may interact with the horizontal routing channels through programmable switches. In addition, a single set of dedicated memory routing tracks may span one or more memory blocks and a plurality of horizontal routing channels. The upper and lower end of the dedicated memory routing tracks may be a set of bus-based bi-directional programmable buffers to connect different blocks of memory to form deeper and/or wider memories. Since each memory structure supports a subset of total configuration modes available, the size of the multiplexer at the input/output of the memories may be reduced to enhance the speed of access to the memories.
Furthermore, the memory structures may be used independently or in combination to implement logic functions. The memory structures may also be multi-port structures, and may be implemented as read only memory (ROM), random access memory (RAM), content addressable memory (CAM), and first in first out (FIFO) structures, for example.